People
Our team at Device Modeling Lab
Faculty
Dr. V. Muthubalan
Research: Microelectronic Device
and Solar Cell Simulation and Modeling
Prof. V. Muthubalan received his M.S. and Ph.D. degrees from Anburn University, United
States of America (USA). His Ph.D. work was concentrated on simulating the radiation
performance of SiGe HBT devices and identification of radiation hardened layout for these
devices using sentarus TCAD, which is being used in space application at NASA. After
completing his Ph.D. in 2007, He joined as Advisory Research Engineer in the semiconductor
Research and Development Center, IBM, Bangalore where he worked on compact modeling of
MOSFET and capacitors for 180 & 90 nanometer bulk and SOI technologies. In 2011, He
joined as Principal Engineer in the TCAD department, Global Foundries, Singapore where he
worked on radiation performance on MOSFET devices. At present, He is working as Associate
Dean-Research in the school of electrical and electronics engineering at the SASTRA Deemed
University. He has been performing extensive research on TCAD simulation of solar cells and
HEMTs in SASTRA Deemed University. He has 18 years of expertise on device physics, TCAD
simulation and compact/analytical modeling.
Contact: muthubalan@ece.sastra.edu
Dr. R. Ramesh
Research: 2D material
Semiconductor Devices
He received a B.E. in Electronics & Communication Engineering from Bharathidasan
University, Tiruchirappalli, M. Tech. and Ph.D from SASTRA Deemed University, Thanjavur. He
is actively working in Modeling of semiconductor devices. He has 20+ years of teaching
experience at several colleges.
Contact: ramesh@ece.sastra.edu
Dr. A. V. Ramachandran
Research: Simulation and
fabrication of organic semiconducting devices
He received the B.Tech. degree in electronics and communication engineering from Anjalai
Ammal Mahalingam Engineering College, Tamil Nadu, India, in 2009, and the M.Tech. degree
from the College of Engineering, Guindy, Anna University Campus. He earned his Ph.D. in
optoelectronics focusing on silicon solar cells from SASTRA Deemed University. During his
Ph.D., he worked as a Junior Research Fellow (JRF) on the Indo-Swiss Project and secured the
CSIR-SRF and the prestigious BASE Internship under Prof. M. A. Alam at Purdue University,
USA. He also worked as a Project Officer in the ARC lab at IIT Madras, a national center of
excellence. He is currently working on SASTRA's TRR and SERB-TARE funded projects on
organic semiconducting devices and teaches courses on device physics, device modeling,
signals and systems, and digital signal processing. His current research interests are the
simulation and fabrication of organic semiconducting devices.
Contact: ramachandran@ece.sastra.edu
Mr. K. Shanmugam
Research: Photovoltaic and Solar
cell
He received a B.E. in Electrical and Electronics Engineering from J.J. College of
Engineering and an M.E. in Energy Engineering from the Institute of Energy Studies, Guindy
Campus. He is actively working in Photovoltaic Cell research. He has 15 years of teaching
experience at several colleges.
Contact: shan@eee.sastra.edu
Ph.D. Students
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Suresh V.
Research: Microelectronics
He received his M.E. in Embedded System Technologies from National Engineering College,
Kovilpatti, and he is currently pursuing his Ph.D. in microelectronics from the School of
Electrical and Electronics Engineering at SASTRA Deemed University, Thanjavur. His research
area includes GaN HEMT, III-V compound semiconductors, pGaN HEMT, and HEMT varactors.
Contact: sureshvenugopal1992@gmail.com
Srinivasa Ramanujam
Research: Microelectronics
He received his MS Electrical Engineering degree from Arizona State University, focusing on
Semi-classical electron transport in Graphene-based nanostructures. Currently, he is pursuing a
PhD in semiconductor device modeling from the School of Electrical and Electronics Engineering at
SASTRA University. His current research includes the simulation of III-V material-based semiconductor
devices for microwave applications.
Contact: dpfi0423011776@sastra.ac.in
SIVA. M. Naveen Sundar
Research: Microelectronic
He graduated with a bachelor’s degree in Physics from Kongu Arts and Science College (Autonomous),
Erode and a Master’s in Physics from Kandaswami Kandar’s College, P.Velur. He is currently pursuing
his PhD in microelectronics from the School of Electrical and Electronics Engineering at SASTRA
Deemed University, Thanjavur and his research focuses on p-GaN-based HEMTs, especially Field-plated
HEMT modeling and simulation.
Contact: dpfi0424011856@sastra.ac.in
Students Alumni
Sundarakumar Muthukumaran
Position: SOC DFT Engineer, Apple Inc. - California, USA.
I graduated with an M.S. degree in Computer Engineering with a specialization in VLSI from the University
of Cincinnati. My thesis focused on the Reverse Engineering of RTL Controllers from Gate-level Netlists.
Currently, I am engaged in the development and enhancement of Apple silicon - SOCs, contributing to both
pre and post-silicon activities. Previously, at the Device Modelling Lab in SASTRA University, I conducted
research on Temperature Sensitivity Analysis of Gate Stack Gate Engineered Dopingless Charge Plasma
Junctionless Transistors using TCAD software.
Contact: sundarmsk4197@gmail.com
Varun Viswanathan
He is pursuing his PhD in Electrical Engineering at Auburn University, AL, USA. He is currently working on Compact Modeling of Semiconductor Devices with industry-standard models for Bipolar Transistor (MEXTRAM). He has worked in the Device Modeling Lab at SASTRA University, Thanjavur while pursuing his B.Tech. in EEE. During his time in the Device Modeling Lab, he worked on TCAD Modeling of Contact Resistance in Solar Cells. He also worked on TCAD modeling of SiGe HBT technology at Auburn University as an exchange student, as part of the Semester Abroad Program during his B.Tech.
Contact: vzv0020@auburn.edu
Srivatsan Srinath
Position: System Design Engineer @ Advanced Micro Devices, Inc. (AMD), Austin, TX, USA
He completed his Master’s in Electrical Engineering from Arizona State University, and he is now working on
the Post-Si Validation and Debug team at AMD on the industry's cutting-edge Centre GPU product. Been a part of
the device modelling lab at SASTRA. He worked on TCAD and compact modelling of SiGe HBTs during his UG in
Thanjavur, and he did his SAP at Auburn University, AL, USA.
Contact: vatsnath@gmail.com
